Total views : 329

Minimization of Area and Power in Digital System Design for Digital Combinational Circuits

Affiliations

  • School of Computing, SASTRA University, Thanjavur, Tamil Nadu, India

Abstract


This paper proposes enhanced parallel adder architectures with low power and reduced area. It includes, design of three different parallel adders such as Ripple Carry Adder (RCA), Carry Look ahead Adder (CLA) and Carry Select Adder (CSA). All three adders are designed in Gate Diffusion Interface (GDI) technique as well as traditional CMOS method. Adder is a basic common combinational digital circuit. Adders are important components in signal processing, image and video processing applications. So it is essential to have compact, low power adder design for these application fields. GDI based digital system design offers reduction in power consumption and area over head. When compared to traditional CMOS based design, GDI uses very less transistor to implement a function. The GDI and CMOS methods are taken in to account for the comparison of design parameters such as design layout, node to node delay, total power dissipation and speed of operation. All three parallel adders are designed in traditional CMOS as well as GDI method. The simulations are done using Microwind2 and DSCH2 analysis software tools and the results between those two types are listed below. This proposed adder circuits can be used in all high speed multipliers and filter designs where low power and reduced area is a major concern.

Keywords

Area, Combinational Circuits, Parallel Adders, Digital Design, Power.

Full Text:

 |  (PDF views: 248)

References


  • Morgenstern A, Fish A, Israel I, Wagner W . GateDiffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. October 2002; 10(5):566-581.
  • Umarani P. A High Performance Asynchronous Counter using Area and Power Efficient GDI T-Flip Flop. Indian Journal of Science and Technology. April 2015; 8(7):622– 628.
  • Chandrakasan AP, Sheng S, Brodersen RW. Low- power CMOS digital design. IEEE J. Solid-State Circuits. Apr. 1992; 27:473–484.
  • Madhusudhan Dangeti, Singh SN. Minimization of Transistors Count and Power in an Embedded System using GDI Technique : A realization with digital circuits. International Journal of Electronics and Electrical Engineering ISSN. September 2012; 2(9):2277-7040.
  • Divya Gupta, Ravindra Prakash Gupta, Raju B.S.N. Analysis of Different CMOS Adders for Power Speed and Area. IJECT. Oct-Dec. 2011; 2(4):120-124.
  • Weste N, Eshraghian K. Principles of CMOS digital design. Reading, MA: Addison-Wesley.
  • Uyemura JP. Circuit Design for CMOS VLSI. Norwell, MA: Kluwer Academic, 1992. p. 88–129.
  • Baker RJ, Li HW, Boyce DE. CMOS circuit design, layout, and simulation. IEEE Press Series on Microelectronic Systems. 205–242.

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.