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A Power-Efficient Multiplexer using Reversible Logic

Affiliations

  • PEC University of Technology, Chandigarh - 160012, Punjab, India

Abstract


The basic concept of reversible circuits is to save energy dissipation in the form of both power and heat in lieu of some additional circuitry. Its use leads to compensating for the garbage bits that will be necessarily generated. Designing a multiplexer can prove to be a very useful block in many complex circuits. A Fredkin gate based multiplexer has been proposed for 180nm, 90nm and 45nm channel lengths. The designed circuit is expected to be fault-tolerant. The W/L ratio has been varied to find the least possible value of power dissipation of the circuit. Substrate-bias voltage of MOSFET can be varied in order to change the threshold voltage value of transistor which helps us in finding the optimum values of driving voltage, input voltage and substrate to bias voltage. Its use is most prominent in an inverter block where tenfold decrease is observed in bulk-driven supply compared to conventional CMOS technology. The value of the bias voltage is found out to be increasing for decreasing channel lengths but bulk-driven voltage supply is not useful in 45nm technology because of increase in transconductance owing to its fixed minimum (W/L) ratio. Delay and power-delay product are also important parameters that have been taken into account. Other important figures of merit like quantum cost, number of garbage outputs, number of gates and quantum depth have also been studied. All the simulations have been done on Cadence tool.

Keywords

Bulk-Driven Technology, Garbage Bits, Power-Delay Product, Quantum Gates, Quantum Cost, Reversible Logic.

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