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Thermal and Energy Efficient RAM Design on 28nm for Electronic Devices

Affiliations

  • Chitkara University, Chandigarh-Patiala National Highway (NH-64), Punjab - 140401, India

Abstract


In this paper an approach is made to design a Thermal and Power efficient RAM for that reason we have used DDR3L, DDR4 and DDR4L memories and four different members of HSTL I/Os standards on 28nm technology. Every electronic device which needs read and write operation requires most energy efficient electronic system and for that very purpose we have designed the most energy efficient RAM. In this design we have taken 3 main parameters, Frequency, Temperature and Voltage. We have done our analysis using the above stated 3 parameters. We have kept the environment constant. For the simulation of the logic, Xilinx is used with Verilog as hardware description language. For different ambient temperatures and I/O standards, we have done our analysis on DDR3L, DDR4 and DDR4L RAMs. When we scaled down from 313.15K to 273.15K, we observed maximum power reduction in DDR3L. We also observed maximum power consumption on chip was from DDR3L as compared to DDR4 and DDR4L. So we used DDR4 and DDR4L in place of DDR3L and observed maximum power reduction in DDR4L. Power consumed by DDR4L on chip is least as compared to DDR3L and DDR4.

Keywords

28nm FPGA, DDR3L, DDR4, DDR4L, Energy Efficient.

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References


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