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Ge/Si Hetero-Junction Hetero-Gate PNPN TFET with Hetero-Dielectric BOX to Improve ION/IOFF
Objective: PNPN TFET is a semiconductor device in which the gate controls the source to channel tunneling current through modulation of band-to-band tunneling. Silicon film thickness is also optimized to remove the kink effect. Methods/ Statistical Analysis: As the Silicon device technology as downsized to nanometers, it experiences certain issues like short channel effects, low ION/IOFF and low Sub-threshold Slope. The hetero-gate dielectric structure is designed with the addition of a hetero-dielectric Buried Oxide (BOX) on the doped substrate for reduction of ambipolar current and improvement of tunneling current at drain and source side respectively. The hetero-dielectric BOX has SiO 2 dielectric below source/channel regions and HfO2 below the drain region. Findings: The proposed device type is of Ge/Si Hetero-junction hetero-gate dielectric with hetero-dielectric BOX PNPN Tunnel FET with low bandgap material at source region increases the tunneling probability and hence improves ION. Various combinations of the simulation where executed with reference to channel, source, drain and N pocket doping for getting the optimized results for Id-Vg characteristics. The entire simulations were done in licensed Cogenda TCAD version 1.7.4 software. The hetero-gate dielectric improves the ION and suppresses the ambipolar current. Also DIBN effect gets reduced because drain current is not varied with changes in Vds(V) values with respect to Vgs(V) values. With the proposed device we obtained the performance parameters as ION=1.24mA/μm, SS=44.66mv/dec and ION/IOFF=3.47×1012. Applications/Improvements: Modeled PNPN TFET had resulted in improved performance in-terms of ION/IOFF ratio, using low band gap material and hence is best alternative over the conventional CMOS devices for the low power and moderate speed applications of FPGA.
Ambipolar Behavior, Band-to-Band Tunneling, Hetero-Dielectric BOX, Hetero-Gate, Power Delay Product (PDP), Sub-Threshold Slope, Tunnel FET
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