Total views : 229

FPGA Specific Real Time Hardware Architecture Implementing Bounding Box Merging Algorithm for Object Detection


  • Department of Computer Science and Engineering, Hamdard University, New Delhi, India and Research Scholar, Uttrakhand Technical University (UTU), Dehradun,, India
  • School of Computational and Integrative Sciences, Jawaharlal Nehru University, New Delhi –110067, Delhi, India


Objectives: This paper focuses on the real time hardware implementation of improved version of Viola Jones algorithm for automatic object detection. Methods/Statistical Analysis: In this regard, A greedy NMS(Non Maximum Suppression) approach has been adopted to develop the bounding box merging algorithm which could suppress the confusing dense grid of overlapping bounding boxes against a threshold value and gives an accurate result and further this algorithm has been transformed in to a real time hardware architecture. Findings: The hardware architecture designed is fully Field Programmable Gate Array (FPGA) based which will take the input coordinates of the image and will process it accordingly by reducing the number of overlapped bounding boxes in real time. Applications/Improvements: Any researcher who is working on automatic object detection can use this hardware architecture as it is in his design and further this architecture itself can be used to create Application Specific IC (ASIC).


ASIC(Application Specific ICs); Bounding box;FPGA;Non-Maximum Suppression(NMS); NMS-FSM(Non-Maximum Suppression Finite State Machine);VGA( Video Graphics Array )

Full Text:

 |  (PDF views: 270)


  • Viola P, Jones M. Rapid object detection using a boosted cascade of simple features. In: IEEE Proceedings of the IEEE Computer Society Conference on Computer Vision and Pattern Recognition, CVPR’01, 2001, 1, p. 511-18.
  • Viola P, Jones MJ. Robust real-time face detection. International Journalof Computer Vision. 2012; 57(2):13754.
  • Raveendra Reddy S, Sakthivel SM. A FPGA Implementation of Dual Images based Reversible Data Hiding Technique using LSB Matching with Pipelining, Indian Journal of science and Technology. 2015; 8(25):1-6.
  • Wang W, Yi-Qing Y. An analysis of the Viola-Jones face detection algorithm. Image Processing On Line, 2014, 4, p. 128-48.
  • Neubeck A, Van Gool L. Efficient non-maximum suppression. In: IEEE 18th International Conference on Pattern Recognition, Hong Kong, ICPR’06, 2006, 3, p. 850-55.
  • Pirsiavash H, Ramanan D, Fowlkes CC. Globally-optimal greedy algorithms for tracking a variable number of objects. In: 2011 IEEE International Conference onComputer Vision and Pattern Recognition(CVPR), RI, 2011, p. 1201-208.
  • Rothe R, Rasmus R, Guillaumin M, Gool LV. Non-maximum suppression for object detection by passing messages between windows. In: Asian Conference on Computer Vision (ACCV), Springer International Publishing: Switerzerland, 2014, 9003, p. 290-306.
  • Hefenbrock D, Oberg J, Thanh NTN, et al.,. Accelerating Viola-Jones face detection to FPGA-level using GPUs. In: 18th IEEE Annual International Symposium on FieldProgrammable Custom Computing Machines, Charlotte, NC, 2010, p. 11-18.
  • Brookshire B, Jon J, Steff Jorgenensen S, Xiao J. In: FPGAbased Pedestrian Detection, Barcelona, 2010, p. 530-537.
  • Hahnle M, Saxen F, Hisung M, Brunsmann U. FPGAbased real-time pedestrian detection on high-resolution images. In: 2013 Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition Workshops, Portland, OR, CVPRW’13, 2013, p. 629-35.
  • Diederichs C, Fatikow S. FPGA-based object detection and motion tracking in micro-and nanorobotics. In: Nanotechnology: Concepts, Methodologies, Tools, andApplications: Concepts, Methodologies, Tools, and Applications, 2014, p. 251-53.
  • Kadali KS, Rajaji L. FPGA and ASIC Implementation of Systolic Arrays for the Design of Optimized Median Filter in Digital Image Processing Applications, Indian Journal of Science and Technology. 2014 Nov; 7(S7):99-103.
  • Zhang Z, Wen-ai W, Zhang B, Cheng YQ. The implementation of VGA display controller with high resolution based on FPGA [J]. Advanced Display. 2006; 9(1):13.
  • Ya-Ping Z, Zhan-Zhuang H. Design of VGA display module based on FPGA. Computer Technology and Development, 2007; 17(6):242-45.


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.