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FPGA Specific Real Time Hardware Architecture Implementing Bounding Box Merging Algorithm for Object Detection

Affiliations

  • Department of Computer Science and Engineering, Hamdard University, New Delhi, India and Research Scholar, Uttrakhand Technical University (UTU), Dehradun,, India
  • School of Computational and Integrative Sciences, Jawaharlal Nehru University, New Delhi –110067, Delhi, India

Abstract


Objectives: This paper focuses on the real time hardware implementation of improved version of Viola Jones algorithm for automatic object detection. Methods/Statistical Analysis: In this regard, A greedy NMS(Non Maximum Suppression) approach has been adopted to develop the bounding box merging algorithm which could suppress the confusing dense grid of overlapping bounding boxes against a threshold value and gives an accurate result and further this algorithm has been transformed in to a real time hardware architecture. Findings: The hardware architecture designed is fully Field Programmable Gate Array (FPGA) based which will take the input coordinates of the image and will process it accordingly by reducing the number of overlapped bounding boxes in real time. Applications/Improvements: Any researcher who is working on automatic object detection can use this hardware architecture as it is in his design and further this architecture itself can be used to create Application Specific IC (ASIC).

Keywords

ASIC(Application Specific ICs); Bounding box;FPGA;Non-Maximum Suppression(NMS); NMS-FSM(Non-Maximum Suppression Finite State Machine);VGA( Video Graphics Array )

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