Total views : 236

A Review on Security in Cache Memories

Affiliations

  • School of Computing, SASTRA University, Thanjavur – 613401, Tamil Nadu, India

Abstract


Objectives: Security in cache memory is a major issue in memory related applications such as smart cards and bio-metric implementations. The objective of this review is to analyze various attacks targeting cache memory and suggest remedial measures to thwart such attacks and assure cache memory security. Methods/Statistical Analysis: Information stored in cache memory can be recovered whenever required. This data is in danger of being hacked by the intruder. Statistical analysis show that attacks such as side channel attacks, timing attacks and power based attacks are adopted to challenge information security in caches. Findings: Discussed solutions involve in the design of secured cryptographic based algorithms, secure aware cache mapping and low power cache design by employing techniques such as code convertors, nested XOR operations, extended Hamming codes and multi-bit clustered ECC. Application/Improvements: Improving and authenticating cache memory security will result in numerous applications involving smart cards and bio-metric applications where secrecy of data is of extreme importance.

Keywords

Cache Memory, Power Based Attacks, Side Channel Attack, Timing Attacks.

Full Text:

 |  (PDF views: 194)

References


  • Brumley BB. Cache storage attacks. Topics in Cryptology.CT-RSA; 2015. p. 22–34.
  • Vinothini S, Segar TC, Vijayaragavan R, Kumar MS. A cubic based set associative cache encoded mapping. IRJET.2015; 2(2):360–4.
  • Kong J, Aciicmez O, Seifert JP, Zhou H. Architecting against software cache-based side-channel attacks. IEEE Transactions Computers. 2013; 62(7):1276–88.
  • Yogesh S, Watile AS, Khobragade K. Design of cache memory with cache controller using VHDL. International Journal of Innovative Research in Science, Engineering and Technology. 2013; 7(2):2914–9.
  • Liu L, Lee RB. Security testing of a secure cache design in hardware and architectural support for security and privacy.HASP’13; 2013.
  • Spreitzer R, Plos T. On the applicability of time-driven cache attacks on mobile devices. LNCS Springer, Heidelberg.2013; 7873:656–62.
  • Mittal S. A cache-coloring based technique for saving leakage energy in multitasking systems. CoRR. 2013; 1309:5647.
  • Yuanyuan Z, Junzhong G. Using counter cache coherence to improve memory encryptions performance in multiprocessor systems. Secure and Trust Computing, Data Management and Applications. 2011; 186:79–87.
  • Page D. Theoretical use of cache memory as a cryptanalytic side-channel. IACR Cryptology ePrint Archive; 2002. p.1–23.
  • Yuemei H, Haibing G, Kai C, Alei L. A new software approach to defend against cache-based timing attacks. Information Engineering and Computer Science Conference (ICIECS); 2009. p. 1–4.
  • Kim K, Soontae S. Reducing area overhead for error-protecting large L2/L3 caches. IEEE Transactions Computers.2009; 58(3):300–10.
  • Wang W, Zhenghong Z, Ruby B, Lee L. New cache designs for thwarting software cache-based side channel attacks.ACM SIGARCH, Computer Architecture News. 2007; 35:494–505.
  • Grabher P, Großschädl J, Page D. Cryptographic side-channels from low-power cache memory in Cryptography and Coding. 11th IMA International Conference; U K. 2007. p.170–84.
  • Bertoni G, Zaccaria V, Breveglieri L, Monchiero M, Palermo G. AES power attack based on induced cache miss and countermeasure. Information Technology: Coding and Computing, ITCC International Conference on IEEE; Italy.2005. p. 586–91.
  • Olanrewaju RF, Al-Qudah DMM, Azman AW, Yaacob M.Intelligent web proxy cache replacement algorithm based on adaptive weight ranking policy via dynamic aging.Indian Journal of Science and Technology. 2016; 9(36):1–7.
  • Kalla AK, Sharma SK. Selective placement of caches for hash-based off-path caching in ICN. Indian Journal of Science and Technology. 2016; 9(37):1–9.
  • Bharathi SM, Sai RV, Saravanan S. Improving the reliability of cache memories using identical tag bits. Indian Journal of Science and Technology. 2016; 9(29):1–5.
  • Vandhana MS, Sai RV, Saravanan S. Cell stability and power reduction using dynamic isolated read static random access memory. Indian Journal of Science and Technology. 2016; 9(29):1–6.
  • Sai RV, Saravanan S, Anandkumar V. Implementation of a novel data scrambling based security measure in memories for VLSI circuits. Indian Journal of Science and Technology.2015; 8(35):1–6.
  • Subha S. An exclusive cache architecture with power saving.Indian Journal of Science and Technology. 2015; 8(33):1–5.
  • Shanmugarathinam G, Vivekanandan K. Performance analysis of cache consistency maintenance in mobile environment using agent technique. Indian Journal of Science and Technology. 2013 Nov; 6(11):1–6.

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.