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Effective Network Parameters on Power Consumption in Networks on Chip

Affiliations

  • Department of Electrical and Electronic Engineering, Eastern Mediterranean University, Famagusta, Mersin 10, Turkey

Abstract


Objectives: To discover the impact of network parameters on power consumption in Networks on Chip (NoCs). Methods: Network on Chip (NoC) has been introduced as a solution for System on Chip (SoC) communication demands. Power consumption becomes a significant component in the NoCs due to the advanced VLSI technology. Findings: In this paper we compare the effect of network parameters such as number of nodes, size of packet length and number of virtual channels on power dissipation in NoCs. Link and total power consumption of NoC with different network parameters with and without using low power encoding algorithm is analyzed. Application/Improvements: A comprehensive evaluation has been accomplished to assess the effect of network parameters in the absence and presence of low power encoding approach on power dissipation in NoCs.

Keywords

Low Power Encoding, Network on Chip, Number of Node, Packet Length, Number of Virtual Channel, Power Consumption.

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References


  • Marculescu R, Ogras UY, Peh L, Jerger NE. Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives.IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems. 2009; 28(1):3–21.
  • Benini L, De Micheli G. Networks on chips: A new SoC paradigm. Computer. 2002; 35(1):70–8.
  • Palma JCS, Indrusiak LS, Moraes FG, Ortiz AG, Glesner M, Reis RAL. inserting data encoding techniques into NoCbased systems. Proceedings of ISVLSI;2007. p.299–304.
  • Malekpour A, Ejlali A. Improving the energy/power consumption of parallel decimal multipliers. Indian Journal of Science and Technology.2014; 7(3):276–81.
  • Selvaraj G, Kashwan KR. Reconfigurable adaptive routing buffer design for scalable power efficient network on chip. Indian Journal of Science and Technology. 2015; 8(12):1–9.
  • Taassori M, Taassori M, Niroomand S, Vizvari B, Uysal S, Hadi-Vencheh A. OPAIC: An optimization technique to improve energy consumption and performance in application specific network on chips. Measurement. 2015; 74:208–20.
  • Taassori M, Niroomand S, Uysal S, Hadi-Vencheh A, Vizvari B. Fuzzy-based mapping algorithms to designnetworkson-chip. Journal of Intelligent and Fuzzy Systems. 2016;31(1):27–43.
  • He O, Dong S, Jang W, Bian J, Pan DZ. UNISM: Unified scheduling and mapping for general networks on chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2012; 20(8):1496–1509.
  • Srinivasan K, Chatha KS, Konjevod G. Linear-programmingbased techniques for synthesis of network-on-chip architectures. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2006; 14(4):407–20.
  • Murali S, De Micheli G. Bandwidth-constrained mapping of cores onto NoC architectures. Proceedings of DATE; 2004. p. 896–901.
  • Hu J, Marculescu R. Energy- and performance-aware mapping for regular NoC architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2005; 24(4):551–62.
  • Hu J, Marculescu R. Energy-aware mapping for tile-based NoC architectures under performance constraints. Proceedings of ASP-DAC; 2003.p. 233–9.
  • Bertozzi D, Jalabert A, Murali S, Tamhankar R, Stergiou S, Benini L, De Micheli G.NoC synthesis flow for customized domain specific multiprocessor systems-on-chip. IEEE Transactions on Parallel and Distributed Systems. 2005; 16(2):113–29.
  • Leary G, Srinivasan K, Mehta K, Chatha KS. Design of networkon-chip architectures with a genetic algorithm-based technique. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2009;17(5):674–87.
  • Chatha KS, Srinivasan K, Konjevod G. Automated techniques for synthesis of application-specific network-onchip architectures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 2008; 27(8):1425–38.
  • Jafarzadeh N, Palesi M, Khademzadeh A, Afzali-Kusha A. Data encoding techniques for reducing energy consumption in network-on-chip. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2014; 22(3):675–85.
  • Taassori M, Mossavi M. Power reduction through adaptive data compression in network on chip architecture. Proceedings of Norchip Conferences; 2009.1–6.
  • Taassori M, Hessabi S. Low power encoding in NOCs based on coupling transition avoidance. Proceedings of DSD Conferences; 2009. p. 247–54.
  • Palesi M, Ascia G, Fazzino F, Catania V. Data encoding schemes in network on chip. IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems. 2011;30(5):774–86.
  • Taassori M, Taassori M,Uysal S. MFLP: A low power encoding for on chip networks. Design Automation for Embedded Systems. 2016;20(3):191–210.
  • International Technology Roadmap for Semiconductors (ITRS) [Internet]. 2011. Available from: http://www.itrs.net.

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