Total views : 327

Design of a Wide Range Hamming Distance Search Circuit using Neuron CMOS Inverters

Affiliations

  • Graduate School of Science and Technology, Tokai University, Kumamoto, Japan
  • Department of Information Electronics, Fukuoka Institute of Technology, Fukuoka, Japan
  • Department of Embedded Engineering, Tokai University, Tokyo, Japan

Abstract


Recently, pattern recognition technologies such as character recognition and finger print recognition are used in various fields. Accordingly, the retrieval technology is becoming important to retrieve the most similar data from a huge database. However, the real-time search is difficult for a software approach, because a digital computer must compare the called data sequentially. To solve this problem, an associative memory has been studied in order to retrieve the reference data which is the most similar to an input data. The associative memory is one of functional memories which is capable of high-speed retrieving for the most similar data by operating parallel. Human brain can retrieve the most similar data to the input data instantly, because it processes information parallel. Accordingly we have focused a neuron CMOS inverter which has characteristics of the brain neuron. In the associative memory, the Hamming distance search circuit is one of the most important circuit to achieve real-time search. In this paper, we propose a wide range Hamming distance search circuit by utilizing neuron CMOS inverters. Unlike conventional circuits, the proposed circuit can retrieve all reference data within a specified Hamming distance.

Keywords

Associative Memory, Hamming Distance, Neuron CMOS Inverter, Time domain.

Full Text:

 |  (PDF views: 230)

References


  • Mattausch HJ, Imafuku W, Kawabata A, Ansari T, Yasuda M, Koide T. IEEE Journal of Solid-State Circuits. 2012; 47(6):1448.
  • Watta PB, Akkal M, Hassoun MH. International Conference on Neural Networks; Houston, Houston, Texas. 1997 Jun 9.
  • Oike Y, Ikeda M, Asada K. Proceedings of the IEEE Custom Integrated Circuits Conference, 2003; San Jose, California. 2003 Sep 21–24.
  • Sasaki S, Yasuda M, Mattausch HJ. 2012 Proceedings of the ESSCIRC; Palais des Congres Bordeaux, France. 2012 Sept 17–21.
  • Shibata T, Ohmi T. A functional MOS transistor featuring gate-level weighted sum and threshold operations. IEEE Trans Electron Devices. 1992; 39(6):1444.
  • Harada Y, Fujimoto K, Fukuhara M, Yoshida M. A minimum hamming distance search associative memory using neuron CMOS inverters. IEE J Trans on Electronics, Information and Systems. 2016; 136(1):36.

Refbacks

  • There are currently no refbacks.


Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.