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FPGA Implementation of High Speed Error Detection and Correction of Orthogonal Codes using Segmentation Method


  • Department of ECE, K L University, Vaddeswaram, Guntur - 522502, Andra Pradesh, India
  • Department of ECM, K L University, Vaddeswaram, Guntur - 522502, Andra Pradesh, India


Background: Our main objective is to improve the error detection and correction capability using orthogonal codes with high security and speed. Statistical Analysis: In order to achieve high speed and security for error detection and correction, we have used cryptography technique. The concept of segmentation is specifically used, as it gives highly secured signal and also reduces the time complexity. Previous study incorporates mapping technique for error detection and correction. Our proposed methodology uses two decoders in place of mapping at the receiver end. This eases the performance and decreases the clock pulses. Findings: The proposed technique will send the k-bit data to encoders and it gets converted into orthogonal codes. The data is then encrypted using encryptor which consists of LFSR. The data is then sent to the receiver and then original data is retrieved using the decoders at the receiver. The multiple bit error correction can be done up to (n/4-1) bits. Here we have compared the delays for 4-bit, 5-bit, 6-bit, 7-bit, 8-bit data. After comparing our technique with the previous study we have found out that the delay time is gradually reduced. Our proposed work is done in n/2+1 comparison, where n represents the bit length of orthogonal codes. Hence this technique achieves 100% multiple bit error detection and error correction rate in the received signal. This technique is simulated in Xilinx software and implement using Field Programmable Gate Array (FPGA). Application/Improvements: This technique can be used for efficient transmission of data in the networks. There is also a wide scope for improvement to limit the bandwidth.


Comparator, Error Detection and Correction, FPGA, LFSR, Orthogonal Codes.

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