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Comparison of Technologies for the Implementation of SBF Decoder for Geometric LDPC Codes
Background/Objectives: The main aim of the proposed design is to optimize the consumption in chip area by improving the error performance by detection and correction. Generally, it is difficult to implement the VLSI based decoding of Geometric LDPC codes because of high complexity and large memory requirements. Methods/Statistical Analysis: In this proposed design architecture we have considered the Soft-Bit Flipping (SBF) algorithm employed here utilizes reliability estimation to improve error performance and it has advantages of Bit Flipping (BF) algorithms. Findings: This proposed design architecture is compared for different technologies using Leonardo spectrum software in Mentor Graphics Tools. We can also obtain the area and delay reports using this tool and optimization of the design is being proposed. Application/Improvement: In future works, this algorithm can be improved with still more security level by having a trade off between performance and data transmission. It can also enhanced by implementing it in real time applications for data decoding and correction, for smaller size datum.
IOB, Leonardo Spectrum, MG (Mentor Graphics), SBF (Soft Bit Flipping).
- Tanner RM. A recursive approach to low complexity codes. IEEE Trans Inf Theory. 1981; 21(5):533–47.
- Gallager RG. Low density parity-check codes. IRE Trans Information Theory. 1962; 8(1):21–8.
- MacKay DJ. Good error-correcting codes based on very sparse matrices. IEEE Trans Inf Theory. 1999; 45(2):399– 432.
- Kschischang FR, Frey BJ, Loeliger HA. Factor graphs and the sum–product algorithm. IEEE Trans Inf Theory. 2011; 45(2):498–519.
- Zhang J, Fossorier. A modified weighted bit-flipping decoding of low-density parity-check codes. IEEE Commun Lett. 2004 Mar; 8(3):165–7.
- Jiang M, Zhao C, Shi, Chen. An improvement on the modified weighted bit flipping decoding algorithm for LDPC codes. IEEE Commun Lett. 2005; 9(1):814–16.
- Fossorier MPC, Mihaljevic M, Imai. Reduced complexity iterative decoding of low-density parity check codes based on belief propagation. IEEE Trans Commun. 1999; 47(5):673–80.
- Palanki R, Fossorier F, Yedidia Y. Iterative decoding of multiple-step majority logic decodable codes. IEEE Trans Commun. 2007; 55(6):1099–102.
- Cho J, Sung S. High-performance and low-complexity decoding of high-weight LDPC codes (in Korean). J Korea Inf Commun. 2009; 34(5):498–504.
- Chen J, Dholakia D, Eleftheriou E, Fossorier MPC. Reduced-complexity decoding of LDPC codes. IEEE Trans Commun. 2005; 53(8):1288–99.
- Liu L, Shi CJR. Sliced message passing: High throughput overlapped decoding of high-rate low-density parity-check codes. IEEE Trans Circuits Syst I. 2008; 58(11):3697–710.
- Ablodun S, Jafar AA, Omar A, Tim OF. Near capacity irregular turbo code. Indian Journal of Science and Technology. 2015; 8(23):110–11.
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