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Adaptive Interplay of DVS and DPM for Power Consumption Reduction in Real-Time Embedded Processors

Affiliations

  • Department of Electrical and Electronics Engineering, Amrita School of Engineering, Coimbatore Amrita Vishwa Vidyapeetham, Amrita University, Coimbatore – 641112, Tamil Nadu, India

Abstract


Objectives: Processors are computing elements of most of the embedded systems. As the technology is growing day by day, processors that are released in the market are mostly embedded processors. Processors are designed to perform concurrent operations and execution at a higher clock rate to meet the performance demands result in large heat dissipation and energy consumption. Thus there is an emphasis on power and energy consumption reduction in real time embedded processors. This work targets to reduce the processor power consumption without violating the real time constraints. Method: In this work, a dynamic power management technique named dynamic counters is employed in real-time system to minimize power consumption. The proposed method facilitates bounding of the events conservatively for effective bounding of future workload. It also employs scheduling ON and OFF time of the devices based on workload bounding at run-time. Simulation analysis is carried out to confirm the performance enhancement of the proposed method. Findings: Energy consumed by the processor increases with the number of event arrivals and switching of modes facilitates significant energy savings. Improvement: Run-time and memory overheads are overcome by dynamic counter technique. Effective bounding of future workload enhances computational efficiency.

Keywords

Dynamic Counters, Dynamic Power Management (DPM), Dynamic Voltage Scaling (DVS), Mode Switching, Real-time Systems.

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