Total views : 681

TG based 2T2M RRAM using Memristor as Memory Element


  • Department of Electronics and Communication Engineering, Birla Institute of Technology (Deemed University), Mesra, Ranchi - 835215, Jharkhand, India


Objective: This article presents a transmission gate based novel 2T2M RRAM using memristor as memory element. Method/Analysis: Simulation results of critical design metrics of proposed 2T2M RRAM cell and conventional SRAM cell are compared. Findings: The proposed 2T2M RRAM cell achieves 1.35 × lower read delays at the expense of 1.02 ×higher write delay than conventional 6T SRAM cell at nominal Vdd. Moreover, being non-volatile it is more power efficient and also saves at least 50% of area. Novelty/Improvement: It is more power efficient and saves 50% of area. Further, being differential in nature, proposed cell is more immune to PVT variation during read operation.


Memristor, Nonvolatile, RRAM, Read Delay, Transmission Gate, Write Delay

Full Text:

 |  (PDF views: 214)


  • Islam A, Hasan M. A technique to mitigate impact of process, voltage and temperature variations on design metrics of SRAM cell. Microelectronics Reliability. 2012 Feb; 52(2):405–11.
  • Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. The desired memristor for circuit designers. IEEE Circuits and Systems Magazine. 2013 May; 13(2):17–22.
  • Hong, Seungbum, Auciello O, Wouters D. Emerging non-volatile memories. Springer US; 2014.
  • Chua LO. Memristor – the missing circuit element. IEEE Transactions on Circuit Theory. 1971 Sep; 18(5):507–19.
  • Strukov DB, Snider GS, Stewart DR, William RS. The missing memristor found. Nature. 2008 May; 453:80–3.
  • Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. Memristor based IMPLY logic design flow. Proceedings of the IEEE International Conference on Computer Design; 2011.
  • p. 142–7.
  • Kvatinsky S, Belousov D, Liman S, Satat S, Wald N, Friedman EJ, Kolodny A, Weiser UC. MAGIC – Memristor Aided LoGIC. IEEE Transaction on Circuit and System. 2014 Nov; 61(11):895–9.
  • Jo SH, Chang T, Ebong I, Bhadviya BB, Mazumder P, Lu W.
  • Nanoscale memristor device as synapse in neuromorphic systems. American Chemical Society, Nano Letters. 2010 Mar; 10(4):1297–301.
  • Linn E, Rosezin R, Tappertzhofen S, Bottger U, Waser R.
  • Beyond von Neumann-logic operations in passive crossbar arrays alongside memory operations. Nanotechnology.
  • Jul; 23(30):305205.
  • Laiho M, Lehtonen E. Arithmetic operations within memristorbased analog memory. 12th International Workshop Cellular Nanoscale Networks and their Applications (CNNA); 2010 Feb. p. 1–4.
  • Mohammad B, Homouz D, Elgabra. Robust hybrid memristorcmos memory: Modeling and design. IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 2013 Nov; 21(11):2069–79.
  • Predictive Technology Model, Arizona State University (ASU) [Internet]. [Cited 2011 Jan 06]. Available from:
  • Kvatinsky K, Friedman EG. Models of memristors for SPICE simulations. IEEE 27th Convention of Electrical and Electronics Engineers in Israel; 2012 Nov. p. 1–5.


  • There are currently no refbacks.

Creative Commons License
This work is licensed under a Creative Commons Attribution 3.0 License.