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Design of 10T SRAM Cell using Column-Line Assist and DTMOS Techniques
Objective: In this article an SRAM cell based on Column Line Assist (CLA) and DTMOS techniques is proposed. Method/Analysis: The CLA scheme is used to provide a dual path during read and write. The availability of an extra path causes read and write delay to be lesser in case of the proposed design when compared to the conventional 10T SRAM cell. Findings: The use of DTMOS scheme causes the threshold voltage of the MOSFETs to be lower, thereby providing faster switching. Our proposed design is compared to the previously designed conventional 10T SRAM cell (CON 10T). It is found that the proposed design shows 1.91 × increments in read current and 43.3% narrower spread in read current. In terms of read delay, an improvement of 1.68 × is observed. Also, the variability is improved by 70%. The read static noise margin (RSNM) of the proposed design is 0.85 × lesser as compared to the CON10T cell. Novelty/Improvement: The write current and write static noise margin increase by 6.2% and 3 × at VDD= 0.4V.
DTMOS and CLA Techniques, Hold Power, Read Delay, Read Current (IREAD), RSNM, Write Delay, WSNM.
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