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Robust Study and Design of a Low Power CMOS CSVCO using 45nm Technology

Affiliations

  • Department of Electronics and Communication Engineering, Birla Institute of Technology, Mesra, Ranchi, India
  • Department of Electronics and Communication Engineering, MMMUT Gorakhpur (UP), India

Abstract


This paper consist of the design and detailed study of a three stage Current Starved Voltage Controlled Oscillator having a very low voltage supply of 1V with low phase noise. The Three stage CSVCO is designed. This work is being done on Cadence virtuoso analog and digital IC design tools with gpdk 45nm CMOS technology process. The voltage supply is taken to be 1V which is low and quite useful according to the latest trends. The center frequency is taken to be 2.4 GHz which is best suitable for satellite and many other applications. The proposed CSVCO consumes low power, low area, low phase noise and high oscillation frequency. The design procedure adopted and the simulation results acquired are illustrated. This CSVCO is suitable for a fast locking PLL, for frequency synthesizer, for clock generation and recovery etc. The results obtained are compared with the previous works and improvements are observed. The Phase noise of the proposed CSVCO is less as compared to the other works.

Keywords

CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor); CSVCO(Current Starved Voltage Controlled Oscillator); low area; low phase noise, PLL (Phase locked loop).

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